SDRAM (or the Synchronous DRAM) works differently than other asynchronous memory types. It is based on the belief that most PC memory accesses are sequentially aligned. It is so designed that it is able to fetch all the bits in a burst as much as possible. It is with SDR RAM that the retrieval of information, in sequential reads, is speeded up considerably.
It is the memory controller that gives the size and location of the memory block. The SDRAM chip is able to supply bits as quickly as the CPU can take. It utilizes a clock so that the timing of the memory chip can be synchronized to the CPU’s system block.
It is due to such features that the SDRAM has an important edge over other memory types, enabling delivery of data, off-chip, at up to 100MHz burst rates. Once the burst gets started, the rest of the remaining bits of the burst length get delivered at a 10ns rate. SDRAMs are able to reduce burst rates to 5/1/1/1 at a bus speed of 66MHz. An 18% theoretical improvement over EDO is there for data transfers of right type.
It is the memory controller that gives the size and location of the memory block. The SDRAM chip is able to supply bits as quickly as the CPU can take. It utilizes a clock so that the timing of the memory chip can be synchronized to the CPU’s system block.
It is due to such features that the SDRAM has an important edge over other memory types, enabling delivery of data, off-chip, at up to 100MHz burst rates. Once the burst gets started, the rest of the remaining bits of the burst length get delivered at a 10ns rate. SDRAMs are able to reduce burst rates to 5/1/1/1 at a bus speed of 66MHz. An 18% theoretical improvement over EDO is there for data transfers of right type.
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